In a phase-locked-loop (PLL), frequency steering is the responsibility of the phase detector circuit that causes the frequency of a voltage controlled oscillator (VCO) that is out of the lock range of the loop to move towards the correct steady-state value. The exclusive-OR logic gate, the most commonly used circuit for high-speed phase detector applications, does not effect frequency steering. Digital phase detectors that have frequency steering on the other hand are too slow for high-speed applications (&gt;100 MHz) when implemented in technology available today.
PLL's with very high (typically greater than 100 MHz) reference frequencies, while not common today, are likely to be used in transmitters and frequency synthesizers in future radio products. The advantage of such loops is a low closed-loop gain, which results in low in-band noise. This is necessary in wide-bandwidth loops for cleanup of VCO noise and reduced interference. Given the above, a need exists in the art for a phase detector with frequency steering that can overcome the above-mentioned limitations.